Kalray Is Pioneering DPU Development with AI-Based Cadence Tools
Scale your data center performance. Discover how Kalray uses Cadence Cerebrus and Innovus to develop high-performance, low-power DPUs for GenAI and 5G.
The Strategic Rise of the Data Processing Unit (DPU) :
In the modern data-centric ecosystem, the Data Processing Unit (DPU) has emerged as a critical third pillar alongside the CPU and GPU. As organizations scale their Data Center Storage to support Generative AI (GenAI), the need for efficient data movement and offloading becomes paramount. Kalray’s DPU architecture is designed to minimize the total system budget and power consumption while maximizing throughput. This is particularly vital for Edge Computing applications like Machine Vision and 5G, where space and energy constraints are most demanding.
A modern DPU is a highly complex ASIC that embeds hundreds of proprietary VLIW Processors and specialized Hardware Accelerators. For the engineering team at Kalray, the primary challenge lies in optimizing these clusters for Power, Performance, and Area (PPA).
To achieve outstanding results in a shortened development window, they have adopted a "software-defined" hardware approach, utilizing a sophisticated Physical Design flow:
1. Physical Implementation : The Cadence Innovus Implementation System is used to handle the massive scaling of the processor clusters, ensuring that timing and performance targets are met across the entire floorplan.
2. Power Integrity : Managing the voltage drop across hundreds of processors is critical for reliability. Cadence Voltus provides the necessary voltage analysis to ensure the chip remains stable even under full-load conditions.
3. Verification and Compliance : To ensure the design is manufacturable and adheres to strict foundry requirements, the Cadence Pegasus Verification System is utilized for comprehensive Design Rule Checks (DRC).
AI-Based Optimization with Cerebrus :
The most transformative element of Kalray’s flow is the integration of Cadence Cerebrus Intelligent Chip Explorer. This AI-Based Optimization engine enables the team to run multiple design iterations autonomously to find the best possible PPA parameters. By leveraging machine learning, Cerebrus can simultaneously optimize timing and area while keeping Power Consumption under control. This ensures that the chip can operate within the desired temperature range even when running at full capacity, a crucial requirement for dense data center environments.
Video Highlights & Timestamps :
0:06 – Achieving High Performance and Low Power with DPU Systems
0:40 – Applications in Data Center Storage and Generative AI (GenAI)
0:53 – Pioneering DPU Development for Edge Computing and 5G
1:08 – Architecture Breakdown: Hundreds of VLIW Processors and Accelerators
1:57 – Physical Design Excellence with Cadence Innovus
2:27 – Ensuring Power Integrity using Voltus for Voltage Analysis
2:32 – Meeting Design Rule Checks (DRC) with Pegasus Verification
2:51 – Optimizing PPA with Cadence Cerebrus AI-Based Solutions
3:12 – Controlling Temperature and Power at Full Capacity
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