MaxLinear Integrates Analog/Digital Design into One Chip with Clarity 3D and EMX Planar 3D Solvers
Discover how MaxLinear integrates complex analog and digital design onto a single die, using Clarity 3D and EMX solvers to solve the thermal and interference challenges of Wi-Fi 7 and 5nm FinFET silicon.
The "Silicon Wall" is real. As the industry moves toward 5nm FinFET nodes, the cost of manufacturing silicon has "gone through the roof." Paolo Mikozzi, Director of SoC and IP Technology, explains that MaxLinear’s unique competitive edge is the ability to integrate heterogeneous analog integrated circuit design with high-speed digital design on the same chip. Whether it is the Puma 8 device for broadband internet connection or the world’s first 5nm CMOS PAM4 DSP for optical infrastructure, every millimeter of silicon must be accounted for.
To manage the high-frequency analysis required for 802.11be (Wi-Fi 7) and 5G ORAN standards, MaxLinear utilizes a tiered simulation approach :
• Chip-Level Precision : The EMX Planar 3D Solver is deployed at the die level. It allows designers to see exact interactions between different parts of the chip and how high-frequency oscillations move across the traces. This is critical for identifying potential signal interference early in the design phase.
• System-Level Co-Simulation : As packages become more sophisticated, chip-level analysis is no longer enough. The Clarity 3D Solver bridges the gap by co-simulating the die with the package and the package with the board. This holistic view ensures that unwanted behaviors don't show up once the silicon comes back from the fab.
• Predictive Accuracy : In the FinFET technology era, accurately predicting chip functionality is the only way to avoid the catastrophic costs of a respin.
MaxLinear’s technical workflow utilizes Cadence tools to turn complex communication theories into production-ready hardware:
1. Block-Level Extraction : Using EMX to simulate individual radios and high-speed analog blocks to determine if multiple radios functioning simultaneously will create interference.
2. Frequency Analysis : Simulating all oscillation frequencies in the design to understand their interaction and minimize cross-talk on the single die.
3. Package-Board Binding : Utilizing Clarity to map the signal paths from the 5nm die through the sophisticated package substrates and onto the system board.
4. Early Identification : Identifying thermal and signal issues months before tape-out to ensure a "Better Product" that meets wifi 7 performance standards.
Video Highlights & Timestamps :
0:09 – Paolo Mikozzi Introduces MaxLinear’s Technological DNA
0:20 – The Unique Integration of Analog and Digital Design on a Single Chip
0:32 – Introducing Puma 8: Advancing Broadband Internet Connection Technology
0:37 – Leading the Wi-Fi 7 Revolution with 802.11be Standards
0:45 – Breaking Barriers: The World’s First 5nm CMOS PAM4 DSP for Optical Infrastructure
1:05 – Integrated Chips for 5G and ORAN Open Radio Access Standards
1:28 – Tackling Critical Challenges in High-Frequency Analysis and Oscillations
1:50 – The Role of EMX Planar 3D Solver and Clarity 3D Solver in Simulation
2:07 – Navigating the High Cost and Complexity of FinFET Technology
2:26 – Managing Unwanted Behaviors and Interference on Silicon
2:51 – Bridging the Gap: Co-simulating the Die, Package, and Board
3:10 – Early Issue Identification for Better Product Reliability
Watch the full video to see the co-simulation results for the die-to-board interface and learn why the Clarity 3D Solver is considered the 'missing link' for optical infrastructure reliability.
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