CORE V VERIF an open source SVUVM environment for RISC V cores
Speaker: Mike Thompson, OpenHW Group
Speaker Biography: Dr. Neel Gala is the CTO of InCore Semiconductors – an early stage fabless startup. Incore is one of the leading provider of silicon proven RISC-V processor IP in India. Dr. Neel received his PhD in Computer Science from IIT-Madras in 2016 and is also one of the creators of the SHAKTI Program initiated at IIT-Madras in 2012 . He was the lead architect of India’s first indigenously designed 64-bit RISC-V chip – codenamed RISECREEK. Dr. Neel also serves as the Vice-Chair of the Compliance Test Group of RISC-V International, published more than 20 international articles and an avid open-source contributor and promoter.
Abstract: CORE-V-VERIF is an open-source project supported by the OpenHW Group. Its goal is to provide an open-source environment and work-flow that can be deployed onto any RISC-V processor core
Recorded at: DVClub Europe Conference 2022
Date: 29th November 2022