Formal Verification
Formal Verification
Formal Property Verification (FPV) approach tailored to Jasper, ensuring rigorous verification of its functional properties. Leveraging techniques like model checking, it offers robust assurances of Jasper's correctness, enhancing reliability in safety-critical applications.
I began my journey in Verification field with training from Maven Silicon Pvt.Ltd Bangalore, diving into the protocols like AXI VIP and UART IP. Later I started as validation Associate Engineer in UST global Pvt.Ltd Bangalore. Got the opportunity in Verification in Silicon Interfaces, Mumbai as Verification Engineer. In silicon interfaces entered into new world called PSS (Portable Test and Stimulus) and Formal Verification, worked on multiple testcases to verify the tool with synopsys.
I began my journey with training from T&VS, diving into the intricacies of AHB and I2C VIP updates. This foundational knowledge propelled me into the dynamic world of IP and SoC design verification at ST, where I honed my skills in integrating Cadence AHB and I2C VIPs. My expertise spans across multiple protocols including AHB, APB, I2C, SPI, SPMI, and AXI, allowing me to tackle diverse challenges in the realm of digital design with precision and efficiency. Building upon this experience, I successfully verified the functionality of LPDDR controller sub-modules