Low Power Verification of RISCV Processor
Low Power Verification of RISCV Processor
The complexity of Next Generation Low Power RISCV has escalated due to the implementation of various low power techniques. These include fine-grained clock gating, power shutoff across multiple domains, body and well biasing, and dynamic frequency and voltage scaling, all aimed at achieving stringent low power objectives for each device mode. The integration of a sophisticated Power Management Controller, power switch fabric, Multi-Core Design, Low Power Subsystem with both Analog and Digital peripherals, diverse Memory types with Retention schemes, and numerous clock and reset sources, has substantially expanded the scope of verification and introduced significant challenges in debugging at the RTL level, as well as timing issues in Gate Level simulations. This paper introduces a comprehensive Low Power Verification Methodology that has been utilized to verify power intent in a next generation RISCV, leveraging advanced verification techniques.
Satinder Paul Singh is a results-driven semiconductor professional with a track record of successfully delivering large-scale semiconductor programs. He thrives in dynamic environments, coordinating with cross-functional and geographically diverse teams at global sites. Singh possesses deep expertise in Hierarchical SoC Architecture, Design, SoC integration, and Core hardening across various product lines, including high-performance processors, 5G, virtual reality gaming engines, Ethernet switches, low-power IoT, and home entertainment devices. Passionate about grasping the intricacies of engineering and business challenges, he formulates strategies, innovates solutions, and leads the market with differentiating products under tight deadlines. Power domain