Is it easy to get started with UVM, or should I use Formal instead?
Is it easy to get started with UVM, or should I use Formal instead?
The Universal Verification Methodology (UVM) is an IEEE standard which provides a library of base classes, a framework and rules that enable complex simulation environments to be created in SystemVerilog. Unfortunately, beginners often struggle to understand the multitude of features provided by UVM. This presentation will introduce a subset of UVM, that makes it easier to get started and will show how these can be used to create a simple UVM testbench. However, a simulation-based approach is not always the best way to verify a design: Formal verification is also possible in SystemVerilog. The presentation will conclude with an overview of formal verification in SystemVerilog and consider how to decide the most appropriate approach to take.