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CORE V VERIF an open source SVUVM environment for RISC V cores
SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification
Why you shouldn’t use Python for Verification
Coverage in Python – pros and cons
TechNES Overview and introduction to The Academy
Functional safety for the world of Autonomous and Zonal
Accelerating Verification with a mix of Automation and AI
Detecting Stimuli with Novel Temporal Patterns to Accelerate Functional Coverage Closure
Advanced Formal Verification and Robust Regression Strategies for Highly Parameterized Designs
End to End Formal Verification of Processors with Fine-Grained Memory Protection
Functional Safety Verification for Automotive Radar SOC’s
Introduction to Verification and SystemVerilog for Beginners
FMEDA-driven Functional Safety Verification for Automotive Semiconductors
Formal Verification
Creating SVA for Formal Verification from Natural Language Specification: iSpec.ai
Trends in Industrial IoT
Trends in HPC/Data Centre
RISC V processor verification with new open standard RVVI based methodology
Is it easy to get started with UVM, or should I use Formal instead?
RISC-V Verification: New Techniques and Approaches for SoC Validation
"Open Source Tools for Verification"
Advancements in AI for Low Power Verification
Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)
Taming formal with intelligent automation?
Mobilise your data to drive predictable verification
Trends in AI/Automation in development
Navigating the verification Complexity with Cadence AI-ML
Extending riscv-dv to suit your specific needs.
Generic Monitor for Mixed Signal Designs
The Ghosts of Challenges Past, Present and Future
Low Power Verification of RISCV Processor
Ensuring my Design Verification is ISO26262 Compliant
System Verilog Training
Agency-directed test generation of AV testing in simulation
Virtual Platform Software Simulation for Enhanced Multi-core Software Verification
Why Reset Domain Crossing Verification is an Emerging Requirement to Accelerate Design-to-revenue
On-Target Testing in the Simulink Model-Based Design Environment
Applying agile techniques to FPGA development
Using Python in Verification
Safety and Security challenges in hardware IP development
RISC V Verif Generators A Configurable ISA warrants a Configurable Verification Environment
Hybrid Simulation, A SystemC -- HDL Co -- simulation
DSP Verification Using MATLAB C Models
Debug with Emulation – Revealing what’s not Visible with Simulation
Building HPC Systems from Mobile Processors: The Mont Blanc Project
Encapsulating Concurrent Assertions in UVM
Getting Started with SystemVerilog and UVM
