FMEDA-driven Functional Safety Verification for Automotive Semiconductors
FMEDA-driven Functional Safety Verification for Automotive Semiconductors
Cadence will present how to create FMEDA at the architectural level, and how to refine for detailed design level. We will show the steps to create the fault list to drive the fault simulation campaign, reducing the fault list, and correctly classifying faults. We will explain how the fault campaign is managed and how Diagnostic Coverage (DC) is measured and fed back to FMEDA to show the relevant ASIL fault metrics can be met.
Pete Hardee is Product Management Group Director for the System and Verification Group (SVG) at Cadence Design Systems. He is responsible for the Jasper formal verification product line as well as SVG’s security and functional safety solutions.