Hybrid Simulation, A SystemC -- HDL Co -- simulation
Recorded at: Verification Futures Conference, India
Date: 13 May 2014
Presenters: Asiful Mondal
Vishal Goel
Title: Hybrid Simulation, A SystemC – HDL Co – simulation
This paper is about Texas Instrument's interest in running hybrid simulation: SystemC virtual platform integrated with RTL models. It describes why TI is interested in such an activity, how it can benefit IP design and verification as well as simulation team. The paper describes a real use case demonstration by TI, where a SystemC based simulator interacts with an IP in RTL form, all under TI's IDE -- Code Composer Studio.