SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification
SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification
Over the last decades HW/SW software systems have become increasingly complex. Today, even small embedded systems are made up of different IP blocks from many vendors and execute complex software stacks consisting of millions of lines of code. This complexity ultimately leads to an increased risk of software bugs and security vulnerabilities that compromise the system’s security and safety. To detect these issues early in the design cycle, full system simulators based on the SystemC TLM-2.0 standard, so called Virtual Platforms (VPs), are the goto tool
Lukas Jünger received his M.Sc. degree in Electrical Engineering from RWTH Aachen University. Afterwards he became a PhD student under the supervision of Prof.
Rainer Leupers at the Institute of Communication Technologies and Embedded Systems (ICE), where his research focus was on the acceleration of full system simulators for early target software development.
In 2022, he co-founded the ICE spin-off company MachineWare GmbH with the mission to bring novel ideas in simulation acceleration from university into industry especially focusing on instruction set simulation and RISC-V