How to create a signal vector in VHDL: std_logic_vector
Learn how to create a data bus in VHDL using the std_logic_vector type. This type can be used for creating arrays of std_logic signals. It is the most commonly used vector type in VHDL.
This is the blog post for this video:
https://vhdlwhiz.com/std_logic_vector/
The syntax for declaring a std_logic_vector signal is:
signal signal_name : std_logic_vector(range) := initial_value;
Of course, you have to replace "signal_name", "range", and "initial_value" with something of your own. The initial value is optional.
A range in VHDL is some kind of integer range. (0 to 9) is a valid range, and so is (9 downto 0). Both of these define 10 bit position. The "to" or "downto" denotes the direction of the range. For example, we can declare vector like this:
signal MySlv : std_logic_vector(9 downto 0);
The above example will yield a 10 bit vector where the LSB (least significant bit) is at the rightmost position.When using "downto", you get the bit ordering which is known as "little endian". This is the preferred way of declaring std_logic_vectors in VHDL. Meaning, that I've never see anyone declare bit vectors using "to".
To specify an initial value, or to assign to a std_logic_vector, we have to enclose our value in double quotes. For example:
MySlv ＜= "0000000001";
The above statement will assign the value '1' to the rightmost bit position, and '0' to all the others.