Out-of-context synthesis in Vivado for inspecting submodule schematics
Sometimes, we want to inspect the synthesized netlists of individual submodules of the design.
We can right-click and "set as top", but that doesn't work if it has too many IO signals. Furthermore, you will always see the IO buffers included in the schematic.
If we want to get rid of these problems, we can use out-of-context synthesis (OOC) to view only the netlist for specific modules in the project.
However, Vivado only supports OOC synthesis on modules that are instantiated using the component instantiation method and does not use the preferred entity instantiation method in VHDL. This video shows how to work around that limitation by using an additional dummy top module.
Finally, I recommend my new course if you want to learn how to use this method to inspect VHDL modules and understand why they produce the logic they produce.
** VHDL synthesis: From code to hardware (Will be released on February 1, 2024):
https://vhdlwhiz.com/product/course-v...
This course teaches you to recognize which digital logic your VHDL code will synthesize into. In the course, we go through 20 VHDL module examples and analyze the elaborated (RTL) and synthesized netlists in the Xilinx Vivado FPGA implementation tool.