Two ways to link processes in different VHDL files
If you want to link processes in multiple VHDL files, you have two options:
• Port map / instantiation
• Signals in a package
I recommend always using regular modules for RTL design and letting all communication between them go through the entity.
For testbenches, on the other hand, it's perfectly OK to use "global signals" defined in a package.
𝗧𝗵𝗲 𝗩𝗛𝗗𝗟𝘄𝗵𝗶𝘇 𝗠𝗲𝗺𝗯𝗲𝗿𝘀𝗵𝗶𝗽 that I mentioned in the video opens on November 1st, 2021.
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