Example of latch inferred from VHDL code
Latches—we usually don't want them in our FPGA designs.
But they don't magically appear in the netlist. They are there because we inadvertently describe their behavior in our VHDL code, and the synthesizer must follow our command and infer them in the netlist.
Here are some articles from the VHDLwhiz blog to help you understand more:
https://vhdlwhiz.com/terminology/latch/
https://vhdlwhiz.com/why-latches-are-...
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The video is a preview of the next course about VHDL synthesis, which I will release in the VHDLwhiz Membership on February 1, 2024. It consists of 19 lessons and helps you recognize which logic elements common VHDL design patterns describe.