Course: Run-length encoding in VHDL
Learn how to implement run-length compression in VHDL! We will create encoder and decoder modules, a self-checking testbench, and implement it on an FPGA board.
Click this link to read more and join:
https://vhdlwhiz.com/product/course-r...
Run-length encoding is a lossless data compression algorithm that’s both simple and ingenious. And it’s well-suited for FPGAs because it works on data streams and doesn’t require many resources.
In the twelve lessons of this mini-course, you will learn how RLE works, how to translate the algorithm to VHDL, and in the end, we will implement it on the Lattice iCEstick FPGA board to see it working in real-time.
You can still use the VHDL code if you have a different board after changing the constraint files. But it’s also OK to only use the simulator because I will show it on my board in the last lesson.
The more advanced learners can benefit from the self-checking testbench that reads and writes BMP image files to verify that the device under test (DUT) is working correctly.