Course preview: VHDL synthesis: From code to hardware
This is a preview showing some lessons in the VHDLwhiz synthesis course.
Click here to read more and see how to access this course:
https://vhdlwhiz.com/product/course-v...
This course teaches you to recognize which digital logic your VHDL code will synthesize into. In the course, we go through 20 VHDL module examples and analyze the elaborated (RTL) and synthesized netlists in the Xilinx Vivado FPGA implementation tool.
Employers often tell me that the biggest challenge when hiring fresh VHDL designers is that the juniors don’t fully understand what kind of logic their VHDL code will produce.
More experienced FPGA professionals usually think in terms of logic rather than algorithms when coding VHDL. But there may be nuances you haven’t thought about that can affect the synthesized netlist, even if you’ve been in the game for a long time.
The course starts with some basic examples but shows more complex patterns and their differences in later lessons. The last seven of the 19 lessons focus on finite-state machines (FSMs).