Self-checking testbench in VHDL
The associated blog post:
https://vhdlwhiz.com/how-to-create-a-...
A self-checking testbench is an automatic testbench. It checks the VHDL module, the device under test, without relying on the developer to check that the output is correct. In the end, a “Test: OK”, or “Failed” will be printed out, indicating that the VHDL module is functioning correct or not.
In this video talk about the importance of having a testbench for each and every module in your design. If you have to revisit you VHDL code in the future, it will be difficult to verify the correctness of the module just by looking at the waveform. You may have forgotten the details about the inner workings of the code. Therefore, your should spend at least as much time creating self-checking VHDL testbenches as you spend writing the RTL modules.