Universal Binary Counter with Upper & Lower Bound Implementation in SystemVerilog
In this video I have designed a highly dynamic counter with clear, load, reset, enable, count up, count down, upper bound and lower bound functions/features.
At the time of making this video I felt under the weather, so my voice may sound a bit different.
Chapters:
0:05 Introduction:
03:07 Modelsim code
15:57 Testing
20:35 More testing
22:44 RTL view of circuit
Book reference: https://www.amazon.com/FPGA-Prototypi...