2 - Bit Comparator by Instantiation in SystemVerilog 👀

Опубликовано: 06 Август 2026
на канале: Jonathan - EE Content
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This video is a continuation of the previous SystemVerilog video in which a 1-bit comparator was made. We can make a 2-bit comparator by instantiating the 1-bit comparator code thereby simplifying our job as a designer.

Chapters
0:00 Introduction
2:44 SystemVerilog Code
8:37 Testbench Code
12:04 Compiling & Testing
15:32 Final Remarks

Disclaimer: At the time of making this video I had practiced verilog and system verilog for about 2 weeks only.

Book reference: https://www.amazon.com/FPGA-Prototypi...