2's Complement(Signed) Adder in SystemVerilog
In this video I have made a parametrized signed adder that can take in 2 inputs of N size bits. This is the parameter that gets passed when instantiating the circuit. This adder performs the addition of 2 binary numbers that are in the 2's complement form. The 2's complement rule is such that it allows a binary numbers to be negative. The adder simply takes in 2 binary numbers and outputs a single binary number. To avoid overflow I have made the output 1 bit larger than that of the inputs. The inputs must be of same size of bits.
Chapters
0:00 Introduction
7:53 ModelSim Code
18:35 More explanation of code
22:18 Testbench
25:41 Testing
29:45 Quartus RTL viewer
Disclaimer: At the time of making this video I had practiced verilog and system verilog for about 4 weeks only.
Book reference: https://www.amazon.com/FPGA-Prototypi...