Broad Verification for a Sequential Circuit in SystemVerilog
The previous video in this series showed how to perform a basic verification method on a sequential circuit. Broad verification, as the name implies, means that we perform a more general test on the sequential circuit. In other words, we create a more robust testbench that checks for correct behavior by itself, without having to look at timing diagrams. The way we achieve this is to append all input variables together into 1 variable. Then we loop through all possible combinations starting from zero to 2^n.
Chapters:
0:00 Introduction
0:30 Sequential Circuit
2:18 Testbench
4:30 Running the testbench
5:30 Browsing testbench results
6:54 Additional testing with increased parameter
8:48 Altering sequential circuit
Correction:
at 03:00, line 56 should just be "if(clr==1)" and line 78, should just be "else if(load == 1)"
The good thing is that this does not negatively affect the outcome of testbench, it now performs the full test without ignoring some iterations. Still, the outcome of the test is identical to that of the video.