2 to 4 Bit Decoder in SystemVerilog
In this video I have designed a decoder according to a given truth table. Enable functions have been implemented.
0:00 Introduction
3:10 module design theory
4:28 2 to 4 bit decoder source code
8:19 2 to 4 bit decoder test bench
11:36 compilation & testing
Disclaimer: At the time of making this video I had practiced verilog and system verilog for about 2 weeks only.
Book reference: https://www.amazon.com/FPGA-Prototypi...