Adder of M inputs Each N Bits Long in SystemVerilog
This is a parametrized 2's complement signed adder of M inputs where each input is N bits long. One can use a previously designed 2 input adder and create a 4 input adder, then use two 4 input adder to create a 8 input adder. This is one of the benefits of SystemVerilog, its the ease of repeated instantiation.
chapters
0:00 Introduction
3:18 ModelSim code 4 input adder
8:26 Testing 4 input adder
10:52 ModelSim code 8 input adder
16:42 Testing 8 input adder
19:40 Quartus RTL viewer of the circuit
Disclaimer: At the time of making this video I had practiced verilog and system verilog for about 4 weeks only.
Book reference: https://www.amazon.com/FPGA-Prototypi...