Verification Methods for a Sequential Circuit in SystemVerilog
I have written a testbench that performs assertions for the purposes of verification. This method of verification is not comprehensive but we can begin to appreciate how difficult verification can be. The first lesson we learn here is that the testbench can get way more involved compared to the circuit that we're testing.
Chapters:
0:00 Introduction
0:36 Testbench
9:03 Testing the testbench
Book reference: https://www.amazon.com/FPGA-Prototypi...