How to print VHDL signal and variables to the simulator console
You can convert boolean, std_logic, and integer types to text by calling the 'image attribute on the type mark.
But that doesn't work with unsigned, signed, and std_logic_vector types. You have to either convert them to integers or use the to_hstring or to_bstring functions from the TEXTIO package to print them as hexadecimal or binary string literals.
In ModelSim, it's easiest to use the report statement to print text.
Click here for more tutorials and articles about VHDL: https://vhdlwhiz.com/