What happens if we implement a VHDL design without constraint files?
Then the FPGA software will choose random pins. That's not very practical if you intend to implement it on the FPGA board.
But still, I often do this. Watch the video to find out why!
Download the ring buffer project from:
https://vhdlwhiz.com/ring-buffer-fifo/
Do you often synthesize standalone modules? Let me know in the comments.