How to delay time in VHDL: Wait For
Learn how to delay time in simulation. Pause the program for a fixed time interval with a line of code. The Wait For statement can be used in simulation to create time delays.
The blog post for this video is:
https://vhdlwhiz.com/wait-for/
The syntax of the Wait For statement is:
wait for [time_value] [time_unit];
The default time value is femtoseconds (fs), but you can specify another time base. Nanoseconds (ns) is the most practical unit to use when working with digital designs that typically run at megahertz clock speeds.
The possible time values are:
femtoseconds (fs)
picoseconds (ps)
nanoseconds (ns)
microseconds (us)
milliseconds (ms)
seconds (sec)
minutes (min)
hours (hr)
Except for Wait statements, all statements in VHDL consume zero time. And by “time”, I mean simulation time. Of course, when a VHDL design is implemented on an FPGA or ASIC, there will be a propagation delay for all operations. But that is outside of the scope of the VHDL language itself. When designing logic in VHDL, it is practical to assume that everything happens instantly.
But what if we take away all Wait statements from our design? What will happen then? Well, if we try to simulate it in ModelSim, it will complain about an “infinite loop “. The simulator recognizes that you probably don't want this, and gives you a compile warning.
The VHDL language is meant for modeling real digital hardware. There needs to be some notion of time for the simulator to be able to run the simulation. The simulator is event driven, and works with time steps. If there wasn't any Wait statements, the simulator would spend forever trying to figure out what happens during the first time step!
The Wait For statement is not synthesizable. This means that it cannot be translated into real hardware. It can only be used in simulation. Therefore, it should only be used in testbenches.
The Wait For statement is normally used for creating stimuli for other modules which are the devices under test (DUT).