How to use Wait On and Wait Until in VHDL
Learn how to cause a VHDL program to wait for signals to change. Wait On and Wait Until are two event-triggered, blocking VHDL statements that are often used in testbenches.
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The syntax for the Wait On statement is:
wait on signal1, signal2, ..
When the program encounters a Wait On statement, it will pause there until any of the specified signals change their value. The Wait On statement can be sensitive to one or several signals at once. When any of them change from one value to another, the program will wake up and continue to the next line.
The syntax for the Wait Until statement is:
wait until [condition]
When the program encounters the Wait Until statement, it will pause until any of the signals mentioned in the condition changes, AND the condition evaluates to true.
Example Wait Until statement:
wait until signal1 = signal2;
The above example will cause the program to pause, even if signal1 is equal to signal2 at the time. The program will then wake up again whenever any of the two signal change, and the condition will then be evaluated for the first time. If they are equal, the program will continue, if not, the program will pause until the next time they change.
If you want the program to pause only if they are not equal, and wait until they are, you have to use an additional If-statement:
if signal1 = signal2 then
wait until signal1 = signal2;
end if;
The Wait On and Wait Until statements are rarely used in RTL (production) code. This is just a convention, because the two statements are synthesizable if used correctly.
It is best to follow this convention and use Wait statements only in testbenches, and sensitivity lists and concurrent statements in RTL code.